The present invention is based on a monolithic integrated planar semiconductor device. From DE-OS No. 32 27 536 a semiconductor device is known designed as a Darlington transistor circuit, wherein the two transistors are monolithically integrated in a planar technique in a common substrate. Thereby, the substrate forms the collector zones of the two transistors. A passivation layer consisting of silicon dioxide is provided on the main surface of the substrate covering this main surface with the exception of contact windows. The base collector junctions of the two transistors are protected by a metal electrode which is present above the passivation layer and which may be characterized as a cover electrode. Moreover, this semiconductor is provided with an integrated voltage divider, whose top is connected with the cover electrode. The electrostatical field which emits from the cover electrode influences the breakdown voltage on the beneath disposed PN-junctions. By means of a suitable selection of the voltage divider an adjustment of the breakdown voltage may be performed, which, however, is very severely dependent from the temperature in the known semiconductor device.